• ==Sorry for the spammy question but the student forums at uni are a bit rubbish. I thought I try my luck here.===

    So I'm going over the past papers for my Computer Hardware exam on Friday and have come across this question. It seems that there is a lot of marks for a relatively simple question.

    I believe the answers to be:

    a) We send data on the data wire which will be read alternating by FF1 and FF2 (due to the inverter on the clock wire between FF1 and FF2), ie, when FF1 reads the data, FF2 does not. The bars over WE indicate that the block is active when the clock is 0V not 5V.

    b) at the first clock change, FF2 is activated and reads 1 off the data wire

    at the second clock change FF1 is activated and reads 1 off the data wire
    

    c) The inverter before FF1 means that the activation is the opposite. FF1 and FF2 read data off the wire at different times.

    What I'm not sure about is whether it matters that the data voltage goes up and down in the middle of the clock phase. I thought that data is only read when the clock changes.

    Is that right?

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Electrical engineers and CompScientists needed for revision

Posted by Avatar for ehren_fried_chicken @ehren_fried_chicken

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